ASIC Power Analysis Engineer

We are seeking a highly skilled ASIC Power Analysis Engineer to join our SoC design team. The ideal candidate will have extensive experience in ASIC power analysis, low-power implementation, and power optimization across the RTL-to-GDSII design flow. This role requires close collaboration with architecture, design, and physical design teams to identify power-saving opportunities, improve analysis methodologies, and drive power-efficient implementations in advanced technology nodes.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

5+ years of experience in ASIC/SoC design with a strong focus on power analysis and optimization.

Hands-on experience with RTL-to-GDSII design flows in advanced technology nodes (7nm and below).

Minimum 3 years of experience with power analysis tools such as:

• Ansys Power Artist
• Cadence Voltus

Experience with Synopsys power analysis flows, including PTPX and PRRTL.

Good understanding of physical design concepts, including:

• UPF
• SPEF
• Clock Tree Synthesis (CTS)

Familiarity with memory architectures such as SRAM, DRAM, Register Files (RFs), and flop-based FIFOs.

Experience or understanding of power optimization techniques for NoC and clocking architectures.

Strong scripting skills in TCL (required).

Proficiency in Python and/or Perl for automation and flow development.

Excellent analytical, problem-solving, and debugging skills.

• Strong written and verbal communication skills with the ability to present technical findings to cross-functional teams.

Please note:

We maintain a zero-tolerance policy toward fraudulent applications. Any candidate found to have provided false information, Misrepresented or fabricated work experience, Falsified educational credentials, Fake or altered identification documents, Fraudulent visa or work authorization documents, Impersonation or proxy interviews, will be immediately disqualified from the hiring process.