Package Design Engineer

Package Design Engineer

Driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience. 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition. Experience in chip package substrate layout, design verification, DFM and taping out for production. Experience in design automation and scripting.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Experience in working with cross functional teams including chip design, SI/PI, and PCB design teams. Experience in 2.5D/3.5D advanced package design. Experience in physical verification flow (LVS, DRC, connectivity). Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD). Ability to write scripts to customize elements of the Cadence or Mentor workflow.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to create complex, high-performance substrate designs, where your goal is to optimize package substrate design for electrical performance, reliability, and assembly. You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation.

Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, which contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits