Senior Signal Integrity Engineer, Platform

Senior Signal Integrity Engineer

Driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. This is a specialized role which requires physical interaction with hardware equipment in a simulated data center environment, utilizing Google labs, power, and safety equipment. Regular development and processing of engineering hardware must be performed on site.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 4 years of experience working in a signal integrity technical environment, or 3 years of experience with an advanced degree.

Preferred qualifications:

Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field. 1 year of experience in technical leadership. Experience with the product development process for mass volume production design, with a focus on signal integrity, power integrity and lab validation. Experience with PCIE, DDR, SATA, ethernet standards, PCB, connector, or cable design and assembly processes, including materials and component selection.

Experience with Allegro, HFSS, SIwave, ADS, Matlab, PowerDC, PowerSI, and scripting for data collection and analysis (e.g., Python, bash). Experience in a lab environment with Serializer/Deserializer (Ser Des) testing and understanding of Ser Des capabilities.

Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. As a Signal Integrity Engineer, you will design and build the systems that are important to our largest and powerful computing infrastructure. You will see those systems from concepts all the way through to high volume manufacturing. You will support the machinery that goes into our data centers affecting millions of Google users.

Support System Signal Integrity (SI) design on data center hardware products. Collaborate with board, chip and system engineers, design partners, and chip vendors, to support system SI design, explore layout and manufacturability tradeoffs, and ensure that product functions as required. Support Application-Specific Integrated Circuit (ASIC), package, board, connector, and cable vendors to develop new interconnect technologies. Participate in system interconnects bring up and qualification, work with test engineers and include configuring chips to ensure adequate margin.

Collaborate with design engineers, Printed Circuit Board (PCB) designers, and system teams to help solve SI issues.