TPU ASIC RTL Design Engineer for AI/ML Acceleration
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-08-08
Listing for:
Socket.dev
Full Time
position Listed on 2026-08-08
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Google is seeking an experienced ASIC RTL design engineer to shape the TPU architecture and AI/ML hardware acceleration. You will drive cutting-edge TPU technology and contribute to the design and verification of complex digital clock control systems, with a focus on timing-critical RTL and DVFS-aware optimizations.
The role requires collaboration with architecture, power, DV, and physical teams to ensure timing closure and scalable performance across Google AI platforms.
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