Design Verification Engineer

Design Verification Engineer

Location:

Sunnyvale, CA (Hybrid; 3 days in office/week) Duration: 6 months with possible extension Pay Range: $73 - $83/hr top

Skills:

System Verilog/UVM testbench development, Functional coverage, assertion-based verification (SVA), and coverage closure, RTL debug (VCS/Xcelium/Questa), Python automation, and power/performance measurement

Company:
Our client is a Fortune 500 multinational technology company headquartered in Menlo Park, CA.

Design Verification Engineer for wearables silicon accelerator IPs — testbench development, coverage-driven verification, RTL debug, and power/performance measurement.

We are seeking a Power Measurement Design Verification Engineer to develop and execute DV test strategies focused on power and performance characterization at the IP and SoC level. This role is critical to enabling accurate pre-silicon power estimation, driving power optimization decisions, and maintaining automated power reporting infrastructure.

• Develop and execute verification plans for RTL blocks/IPs across the subsystem.
• Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.
• Drive functional coverage and assertion (SVA) closure; run and triage regressions.
• Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
• Build power/perf dashboard for tracking and publishing.
• Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.
• Contribute to automation of verification/regression and power/performance measurement flows (Python).

• Proven System Verilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).
• Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.
• Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).
• Working knowledge of RTL design principles and digital design fundamentals.
• Proficiency in Python (or Perl) scripting for automation.

• Experience with power measurement tools — Prime Time PX (PTPX) or equivalent (e.g., Prime Power).
• Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).
• Formal verification and/or emulation (Palladium / Zebu) experience.
• Familiarity with the RTL-to-GDSII flow.
• Data analysis / ML approaches for coverage or debug triage.

• System Verilog / UVM testbench development.
• Functional coverage + assertion-based verification and coverage closure.
• RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.

• BS in Electrical/Computer Engineering or Computer Science required.
• MS preferred (not required).

Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position.

These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation. Benefits summary:
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate or annual salary only, unless otherwise stated. In addition to base compensation, full-time roles are eligible for Medical, Dental, Vision, Commuter and 401K benefits with company matching. IND
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