Core Engineering - Design Engineer III

Core Engineering - Design Engineer III

This position is for a Design Verification engineer focused on wearables silicon accelerator IPs. The role involves testbench development, coverage-driven verification, RTL debug, and power and performance measurement. The successful candidate will work with a small team to build and run test benches, analyze coverage, debug failures, and measure power and performance.

Location:

Sunnyvale, California (Partial Remote) 3 days / week onsite Compensation: $70- $80 Hourly

Key Responsibilities

• Develop and execute verification plans for RTL blocks and IPs across the subsystem.
• Build and maintain System Verilog/UVM test benches, and write directed and constrained-random tests.
• Drive functional coverage and assertion (SVA) closure, and run and triage regressions.
• Perform power and performance measurement across design stages using specified tools and correlate results with post-silicon data.
• Build a power and performance dashboard for tracking and publishing results.
• Debug RTL failures using waveform tools and provide feedback to the design and verification teams.
• Contribute to the automation of verification, regression, and power/performance measurement flows using Python.

Required Qualifications

Education:

A Bachelor of Science in Electrical/Computer Engineering or Computer Science is required.

Technical

Skills:

• Proven System Verilog and UVM verification experience, including testbench architecture, sequences, and drivers/monitors.
• Experience with functional coverage, constrained-random, and assertion-based verification (SVA) and coverage closure.
• Strong RTL debug skills with industry simulators (VCS, Xcelium, or Questa) and waveform tools like Verdi.
• Working knowledge of RTL design principles and digital design fundamentals.
• Proficiency in Python or Perl scripting for automation.

Preferred Qualifications

• An MS in a relevant field is preferred.
• Experience with power measurement tools such as Prime Time PX (PTPX) or equivalent.
• Experience with low-power or power-aware verification (UPF, power-aware simulation) in advanced nodes (7nm and below).
• Formal verification or emulation (Palladium / Zebu) experience.
• Familiarity with the RTL-to-GDSII flow.
• Experience with data analysis or machine learning approaches for coverage or debug triage.

Everforth Apex Systems is an equal opportunity employer. We do not discriminate or allow discrimination on the basis of race, color, religion, creed, sex (including pregnancy, childbirth, breastfeeding, or related medical conditions), age, sexual orientation, gender identity, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, disability, status as a crime victim, protected veteran status, political affiliation, union membership, or any other characteristic protected by law.

Everforth Apex will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable law.