Senior RTL Design Engineer, TPU SoC for AI Acceleration
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-08-10
Listing for:
Socket.dev
Full Time
position Listed on 2026-08-10
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer, Test Engineer
Job Description & How to Apply Below
Google in Sunnyvale, CA is seeking a senior ASIC design engineer to shape the TPU architecture and AI/ML hardware acceleration. You will contribute to SoC-level RTL design for data center accelerators, collaborating with software and system hardware teams.
You will develop System Verilog RTL, verify complex digital designs, and partner with power/architectural groups to meet timing and power targets.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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