Senior Design and Integration Engineer, Cloud TPU

Senior Design and Integration Engineer, Cloud TPU

Sunnyvale, CA, USA. Level: Mid.

Shape the future of AI/ML hardware acceleration by driving the design, optimization, and integration of next‑generation Tensor Processing Units (TPUs). Work closely with Verification, Physical Design, Validation, and Firmware teams to deliver cutting‑edge hardware for Google’s AI workloads.

• Define and document the microarchitecture for digital designs within the TPU.
• Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to meet timing, area, power, and manufacturability goals.
• Drive critical power optimization and automation initiatives across all on‑chip‑network components and subsystems.
• Support post‑silicon validation and hardware debugging to ensure successful deployment.
• Lead the development and enhancement of internal design tools, flows, and engineering methodologies.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience in RTL design.
• Experience with digital and microarchitecture design.
• Cross‑functional experience with DV and PD teams.
• Experience optimizing for performance, power, and area.

• Master’s degree or PhD with emphasis on computer architecture.
• 10 years of RTL design experience.
• 4 years of experience in power optimization and use of tools such as Power Artist and PTPX.
• Experience with linting, CDC, RDC, LEC, and scripting languages (Python or Perl).
• Experience optimizing RTL solutions, design methodologies, and automating front‑end engineering flows.
• Experience in design automation, RTL architecture, and ASIC synthesis flows.

US: $163,000 - $237,000 (USD) + 15% bonus target + equity + benefits.

Learn more about benefits at Google.

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