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Senior IC Packaging Engineer - 2.5D/3D & TSV Expert
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-08-22
Listing for:
Avicena Tech
Full Time
position Listed on 2026-08-22
Job specializations:
-
Engineering
Packaging Engineer
Job Description & How to Apply Below
Avicena is seeking a Senior IC Packaging Engineer in Sunnyvale, CA to lead architecture, design, and development of advanced semiconductor packaging solutions including 2.5D/3D IC, SiP, flip chip, and WLP. You will own TSV reveal processes, C4 bumping flows, and drive process control plans and yield improvements across optical engine packaging modules.
The role requires 5+ years in packaging or wafer fab engineering, strong cross-functional collaboration, and hands-on experience with metrology
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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