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TPU SoC Architect — RTL Design for AI Acceleration
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-08-22
Listing for:
Google Inc.
Full Time
position Listed on 2026-08-22
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer
Job Description & How to Apply Below
Google is shaping the future of AI/ML hardware acceleration. As a Soc Design Engineer on the TPU team, you’ll contribute RTL design for data center accelerators, implement global bus architectures, and collaborate with ASIC teams to meet timing, power, and manufacturability goals.
You’ll own microarchitecture definitions, write high-quality System Verilog RTL, and partner with Verification and Physical Design to ensure correctness and efficiency in a highly cross-functional environment.
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