SOC Validation Engineer

HCLTech is looking for a highly talented and self- motivated SOC Validation Engineer to join it in advancing the technological world through innovation and creativity.

Job Title: SOC Validation Engineer

Job REQ

Position Type:
Full Time

We are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems — including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs — with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.

• Develop comprehensive verification and validation plans for SoC-level IP subsystems including Clock Generation/Distribution (PLLs, clock muxes, dividers),
  Reset Architecture
  , Ethernet MAC/PHY
  , and I/O interfaces (GPIO, I2C, SPI, UART, JTAG)
• Create and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level
• Verify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior
• Validate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces
• Perform functional coverage analysis and drive coverage closure across IP blocks
• Collaborate with design and architecture teams on RTL debug, assertions, and specification reviews
• Execute validation on emulation/FPGA prototyping platforms (Palladium, Veloce, Protium) for early software/firmware integration
• Bring up and validate SoC IPs on first silicon and platform boards
• Develop and execute post-silicon test plans covering:
• Clock: PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions
• Reset: Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown‑out detection
• Ethernet: Link bring-up, auto‑negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 time stamping
• Debug silicon failures using oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx
  , and embedded trace tools
• Perform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams
• Characterize IP performance under varying voltage, frequency, and temperature (VFT) conditions
• Develop and maintain automated test frameworks for regression and production testing
• Collaborate with platform, firmware, BSP, and driver teams on system-level integration and debug

• Author and maintain validation documentation: test plans, debug reports, coverage metrics, and known‑issue databases
• Develop Python/Perl/Tcl scripts for test automation, log parsing, and result analysis
• Participate in silicon bring‑up triage, failure analysis, and bug review meetings
• Mentor junior engineers and drive process improvements in validation methodology
• Interface with IP vendors for third‑party IP integration, compliance, and issue resolution

• Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field
• Experience: 4–10+ years in SoC validation (pre‑silicon and/or post‑silicon)
• Deep understanding of SoC architecture and IP integration concepts

• Pay Range Minimum: $78000/annum
• Pay Range Maximum: $148000/annum

HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to  for investigation.

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law.

This role may also be eligible for performance‑based bonuses subject to company policies.

In addition, this role is…