ASIC Engineer, Design Verification
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listing for:
Meta
Full Time
position
Listed on 2026-08-22
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 178000 - 250000 USD Yearly
USD
178000.00
250000.00
YEAR
Job Description & How to Apply Below
Summary
Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to drive verification strategy and execution for custom silicon powering Meta's data center infrastructure. In this role, you will lead the end-to-end verification of complex IP blocks and SoCs designed for AI/ML acceleration, networking, and video processing workloads. You will architect scalable UVM-based verification environments, define coverage models, and partner with design, emulation, and post-silicon validation teams to achieve first-pass silicon success across Meta's infrastructure ASIC portfolio.
Required
Skills
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design qualityDevelop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industryMinimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience8+ years of hands‑on experience in System Verilog/UVM methodology and/or C/C++ based verification8+ years experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologiesExperience in one or more of the following areas along with functional verification: SV Assertions, Formal, EmulationExperience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsExperience in architecting and implementing Design Verification infrastructure and executing the full verification cyclePreferred Qualifications
Experience with compute and/or memory subsystem and/or collective functional and performance verificationExperience with verification of ARM/RISC-V/GPU based sub-systems or So Cs Experience in development of UVM based verification environments from scratchPrior experience with fullchip or package-level integration projectsExperience working across and building relationships with cross-functional design, model and emulation teamsFamiliarity with host and system-level concepts for functional verificationExperience with chiplet based architectures and package-level integration verificationPublic Compensation
$178,000/year to $250,000/year + bonus + equity + benefits
Industry
Internet
Equal Opportunity
Meta is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics.
We also consider qualified applicants with criminal histories, consistent with applicable federal, state, and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at
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