RTL Design Engineer, TPU

Google, Sunnyvale, CA, USA

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with scripting languages.

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• 8 years of experience in ASIC design.
• Experience interacting with software, system hardware, and other cross‑functional teams.
• Experience with chip management, clocking, reset, and peripherals such as I2C, SPI, UART.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.

• Design RTL Intellectual Property (IP) focusing on management and control subsystem.
• Develop System Verilog RTL to implement logic for ASIC products according to coding and quality guidelines.
• Collaborate with architecture and power teams to evaluate features and their impact.
• Collaborate with design validation teams to create test plans, verify, and debug RTL.
• Collaborate with physical design teams to ensure design meets physical requirements and timing closure.
• Build a global understanding of accelerator development from concept to production.
• Coordinate and co‑design with software and system hardware counterparts.
• Leverage design and verification expertise to verify complex digital designs, focusing on TPU architecture and its integration within AI/ML‑driven systems.

US compensation: $163,000–$237,000 (USD) + 15% bonus target + equity + benefits.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants.

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