ASIC Engineer, Performance Architecture and Modeling

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads  an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure. In this role, you will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience8+ years of experience in ASIC design, silicon engineering, or a related technical field
• 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs
• Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools
• Experience developing cycle‑accurate or transaction‑level performance models using C++ and SystemC for complex digital systems including processors, memory subsystems, or high-speed interconnects
• Experience with performance analysis of data center, AI accelerator, or high‑performance computing workloads on custom silicon
• Experience defining microarchitectural specifications and driving cross‑functional alignment across architecture, RTL, and physical design teams
• Experience with assembly programming languages, and compiler technologies
• Experience with hardware description languages (e.g., System Verilog, VHDL) and simulation environments used in ASIC development flows
• Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs
• Familiarity with post‑silicon performance validation and model-to‑hardware correlation methodologies
• Experience developing Python‑based automation pipelines for simulation orchestration, regression testing, and performance data analysis
• Experience with GPU, machine learning, multi‑threaded programming paradigm
• Experience with high‑level synthesis, power‑performance‑area trade‑off analysis, or PPA‑driven microarchitectural optimization