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ASIC Verification Engineer Speed DV & Formal
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-08-29
Listing for:
Avicena Tech
Full Time
position Listed on 2026-08-29
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Job Description & How to Apply Below
Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You will develop robust verification environments, using UVM, System Verilog, and Python scripting, to ensure functionally correct, high-performance digital ICs for silicon photonics and optical interconnect solutions.
The ideal candidate has 3+ years of ASIC/SoC DV experience, strong debugging skills, and a track record of regression and coverage closure.
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