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Formal Verification Engineer — RTL & Tools Lead
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-08-30
Listing for:
Synopsys
Full Time
position Listed on 2026-08-30
Job specializations:
-
Engineering
Test Engineer
Job Description & How to Apply Below
Synopsys is seeking a Senior Formal Verification Engineer to lead deployments and optimize verification workflows for customer designs in Sunnyvale. You will diagnose tool performance issues, tailor methodologies, and train customers on new features, working closely with R&D to align product directions.
Strong RTL/Verilog/VHDL, scripting, and formal verification experience are required. You will engage with customers to drive adoption, reduce bottlenecks, and scale verification across SoCs,
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