Hardware Engineer

Ascendion is a full service digital engineering solutions company. We make and manage software platforms and products that power growth and deliver captivating experiences to consumers and employees. Our engineering, cloud, data, experience design, and talent solution capabilities accelerate transformation and impact for enterprise clients. Headquartered in New Jersey, our workforce of 6,000+ Ascenders delivers solutions from around the globe. Ascendion is built differently to engineer the next.

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• We are seeking an experienced EE Validation Engineer to support hardware validation of next-generation smart glasses, working closely with the validation lead.
• In this role, your primary focus will be monitoring validation progress, reviewing CM test reports, analyzing failures, and coordinating with EE design partners to drive issues to closure.
• You will also guide CM engineers on measurement procedures and perform hands-on PI/SI debug when needed.
• While you must possess strong hands-on measurement skills, the majority of your time will be spent interpreting data, tracking issues, and ensuring problems are resolved efficiently.
• You will not own final validation decisions, but you are expected to be technically strong enough to flag risks, recommend actions, and keep execution on track under the lead's direction.

Issue Tracking & Closure (Primary Focus ~60%)Review CM-generated validation reports: verify data quality, flag anomalies, confirm pass/fail criteria are correctly applied Analyze validation failures; determine whether issues are measurement errors, design defects, or assembly quality problems Coordinate with EE design partners to present data, propose root cause hypotheses, and support corrective action decisions Track open issues through resolution; ensure fixes are validated and closed in a timely manner Facilitate communication between CM, EE design, layout, and firmware teams to keep issues moving Maintain issue tracker and provide regular status updates to the FTE validation lead Monitor overall validation progress against milestones;

elevate risks and blockers early.

Develop clear, repeatable test procedures (SOPs) that CM technicians can execute independently Train and guide CM engineers/technicians on proper measurement techniques, probe placement, fixture usage, and data collection Define probe points and measurement access strategy; communicate to CM with annotated layout markups Provide real-time technical guidance to CM when measurements yield unexpected results Establish clear acceptance criteria and escalation paths for CM to follow, in alignment with the FTE validation lead Hands-On Measurement & Debug (~20%) Perform PI/SI measurements that require senior-level judgment (e.g., first article bring-up, intermittent failures, subtle noise sources) Validate CM measurement setups by performing correlation measurements Debug escalated issues that CM cannot resolve independently Develop new measurement methodologies and fixtures for novel circuits or challenging probe access Support prototype bring-up and characterization during build phases.

Power Integrity (PI) DC-DC converter characterization: line/load regulation, efficiency, transient response, output ripple/noise Power sequencing validation and timing verification against IC specifications Power rail stability under varying load conditions; current profiling Battery charging circuit validation: charge profiles, protection, thermal limits PDN concepts: ground bounce, decoupling strategy, voltage droop analysis Signal Integrity (SI) High-speed interface measurement: MIPI CSI, SPI, I2C, I2S/PDM, USB, UART Signal quality assessment: rise/fall times, overshoot/undershoot, ringing, eye diagrams Crosstalk, reflections, and impedance discontinuities on flex/rigid-flex assemblies.

level correlation with physical-layer signal issues Schematic & Layout Competency Read and interpret multi-page schematics to understand circuit topology, power trees, and signal routing Review PCB layout (rigid and flex) to identify optimal probe locations and debug access points Assess…