Sr R&D Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent years turning ASIC designs into working FPGA prototypes, and you know the difference between RTL that compiles and RTL that actually runs reliably across multiple FPGAs  challenge excites you: partitioning a design that was never meant to be split, closing timing on a path that crosses three SLRs, or debugging a reset issue that only shows up in hardware after two hours of runtime.

You are equally comfortable writing System Verilog that synthesizes cleanly and Python scripts that automate the tedious parts of your workflow. When a bring-up fails, you reach for the logic analyzer, the scope, and the source code in that order, and you do not stop until you understand why. You have learned that production-quality tools matter as much as production-quality RTL, and you build both.

Multi-FPGA systems do not intimidate you. Clock domain crossings, inter-FPGA communication, resource utilization analysis, these are problems you have solved before, and you know how to solve them again under new constraints. You work well with hardware teams, software teams, and manufacturing teams because you understand that your prototype is only useful if it helps someone else move forward.

At Synopsys, you will work on HAPS prototyping platforms that enable real customer designs to run before silicon exists. The problems are hard, the systems are real, and what you build will directly affect how quickly our customers can validate their next chip.

• Develop FPGA-optimized implementations for HAPS platforms, addressing capacity limits, timing constraints, and multi-FPGA partitioning challenges
• Own the full FPGA development cycle from RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices
• Drive board and system bring-up for HAPS prototyping hardware, including functional validation, performance characterization, signal integrity testing, and root-cause debug of complex hardware and RTL issues
• Develop production-ready test frameworks and automation tools using Python and C/C++ to validate high-speed interfaces, run PRBS testing, analyze eye diagrams, and measure jitter and link margins
• Build and maintain multi-FPGA solutions including partitioning strategies, inter-FPGA communication protocols, clock distribution networks, and reset architectures that work reliably across device boundaries
• Debug RTL, timing, clocking, and integration issues across simulation, emulation, and physical hardware using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and spectrum analyzers
• Collaborate with architecture, hardware, software, manufacturing, and verification teams to deliver prototyping solutions from concept through production deployment

• Enable customer ASIC designs to run on HAPS platforms months before silicon is available, directly accelerating their validation schedules and reducing risk
• Deliver FPGA implementations that close timing, meet performance targets, and run reliably in production test environments, reducing debug cycles and improving product quality
• Build automation tools and workflows that make FPGA bring-up faster and more repeatable for the entire HAPS Production Test Team
• Solve complex multi-FPGA partitioning and communication challenges that unlock prototyping for designs that would otherwise be too large or too fast for a single device
• Identify and resolve signal integrity, timing, and hardware issues that would otherwise delay product releases or cause field failures
• Create test frameworks and validation infrastructure that catch issues early and give manufacturing teams confidence in what they are shipping
• Contribute technical expertise and design documentation that raises the bar for how the team approaches FPGA development, bring-up, and production test

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of hands-on FPGA and RTL design experience
• Expert-level proficiency in System Verilog and Verilog for RTL design, with deep understanding of digital design fundamentals, clocking architectures, reset strategies, clock domain crossing, and timing analysis
• Extensive experience with AMD/Xilinx FPGA synthesis, place-and-route, and timing closure using Vivado, including optimization for resource utilization, SLR crossings, and routing congestion
• Strong programming skills in C/C++ and Python with a proven track record of developing production-quality software, automation frameworks, debug…