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ASIC Design Engineer II: -Speed Networking Chips

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: Hewlett Packard Enterprise
Full Time position
Listed on 2026-09-08
Job specializations:
  • Engineering
    Hardware Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 106000 - 214000 USD Yearly USD 106000.00 214000.00 YEAR
Job Description & How to Apply Below
Position: ASIC Design Engineer II: High-Speed Networking Chips

Hewlett Packard Enterprise in Sunnyvale, California, is seeking an ASIC Design Engineer 2 to join our fast-paced chip design group. This onsite role focuses on building high-speed ASICs from specification to netlist, with opportunities to explore design, verification, or timing closure.

You will develop RTL in System Verilog, verify functionality, and partner with PD to ensure timing targets are met, while leveraging cutting-edge EDA tools and a culture that values innovation and collaboration.

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