Principal Application Engineer- Timing Sign Off

Principal Application Engineer
- Timing Sign Off

Job

18326

City

Sunnyvale

State/Province

California

Date Posted

04-Aug-2026

Job Category

Job Subcategory

Applications Engineering

Employee

No

Base Salary Range: $160000 - $ 240000

Job Description and Requirements

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent a decade or more in the trenches of timing signoff, and you know that the moment a customer says "we're ready to tape out" is when the real work begins. The difference between a chip that ships on schedule and one that doesn't often comes down to someone who can diagnose a cryptic timing violation at 2 a.m., propose a workaround that doesn't blow up the methodology, and explain the tradeoff clearly enough that the design lead trusts it.

You are fluent in Prime Time the way some people are fluent in a second language. You have debugged enough corner case failures to know when a problem is tool behavior, user error, or an actual design issue, and you can tell the difference in about ten minutes. When a customer hits a wall three days before tapeout, you do not panic.

You ask the right questions, pull the right data, and find a path through.

You have worked closely enough with product teams to know what belongs in a feature request and what belongs in a methodology guide. Mentoring comes naturally to you because you remember what it felt like not to know, and you care about making the next engineer better. At Synopsys, you will work with the most advanced chip designs in the world, and what you enable will directly determine whether those chips make it to market.

• Support customer tapeouts for leading edge designs, diagnosing timing, power, and signoff issues in Prime Time, Prime Shield, Prime Closure, and Prime Power under real schedule pressure
• Deploy newly developed signoff features with customers, working through beta testing, adoption blockers, and methodology integration in live design environments
• Evaluate customer requirements and translate them into actionable enhancement requests for the product development team, backed by real use cases and data
• Build and deliver technical training content, demos, and methodology documentation that help customers and internal teams use signoff tools correctly and confidently
• Replicate, debug, and escalate product issues, working across engineering, R&D, and account teams to resolve problems that affect customer schedules
• Mentor applications engineers and customer design teams on timing signoff best practices, corner case handling, and flow optimization
• Align technical enablement plans with account strategy, ensuring that the right customers get the right support at the right stage of their design cycle

• Enable customers to tape out complex, leading edge designs on schedule by solving signoff problems that would otherwise delay or derail their projects
• Influence the development roadmap for Synopsys signoff tools by surfacing real customer pain points and advocating for the features that matter most
• Accelerate adoption of new signoff capabilities across the customer base, turning beta features into production workflows that improve design quality and turnaround time
• Reduce escalations and support load by creating training materials and methodology guides that help customers solve problems independently
• Strengthen customer relationships and renewals by being the engineer they trust when the stakes are highest
• Raise the technical capability of the broader applications team through mentorship, knowledge sharing, and methodology leadership
• Shape how the semiconductor industry approaches timing signoff for the next generation of AI, 5G, automotive, and high-performance computing designs

• Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field
• 10+ years of hands-on experience with timing analysis and signoff tools, flows, and methodologies in a customer-facing or product development role
• Deep working knowledge of Prime Time, and direct experience with at least two of the following:
  Prime Shield, Prime Closure, Prime Power
• Demonstrated ability to debug complex signoff issues under tapeout pressure and propose solutions that balance accuracy, runtime, and methodology constraints
• Strong understanding of static timing analysis fundamentals, including multi-mode multi-corner analysis, OCV, AOCV, path-based analysis, and signoff closure techniques
• Experience with adjacent tools like StarRC, Red Hawk-SC, Spice, Hspice, or Prime Sim is a strong plus
• Proven ability to work effectively across…