Senior SoC Physical Design Engineer - RTL-to-GDSII
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-09-09
Listing for:
Value Innovation Labs
Full Time
position Listed on 2026-09-09
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
Value Innovation Labs is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for low-power SoCs on advanced nodes. You will drive the full physical design flow from synthesis to GDSII, including floor planning, placement, CTS, routing and timing closure.
You will handle SDC constraints and UPF promotion, develop automation flows with Tcl, Python and Shell, and mentor junior engineers while collaborating on design closure and signoff across the SoC hierarchy.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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