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Machine Learning SoC Architect

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: Meta
Full Time position
Listed on 2026-09-11
Job specializations:
  • Engineering
    Hardware Engineer, Systems Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 300000 USD Yearly USD 300000.00 YEAR
Job Description & How to Apply Below

Meta is seeking a Machine Learning SoC Architect for its Silicon Engineering organization responsible for building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads  an ASIC Engineer specializing in architecture, performance and modeling, you will define and drive the architectural definition, performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's Data Centers.

In this role, you will own ASIC architecture specification, establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with other silicon, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • Experience and knowledge of Computer Architecture concepts such as microprocessor architecture, memory systems, on-chip interconnection networks, hardware/software partitioning etc
  • 12+ years of prior experience in defining and delivering multiple high performance ASICs into production, with focus on architecture definition and performance analysis
  • Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs
  • Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools
  • Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon
  • Experience defining architecture and microarchitectural specifications and driving cross‑functional alignment across architecture, RTL, and physical design teams
  • Familiarity with post‑silicon performance validation and model‑to‑hardware correlation methodologies
  • Programming in C or C++ with knowledge of mapping hardware algorithms to efficient C/C++ code
  • Master's or PhD degree in Electrical Engineering, Computer Engineering or related field
  • Domain knowledge in one or more of power/performance tradeoffs, ML networks, ML frameworks such as Pytorch
  • Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs
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