STA & Custom Logic Design Engineer

Description

In this role, you will perform timing analysis on custom design circuits, delivery timing views to integration teams, as well as develop custom logic design in analog/mixed-signal circuits. You will work closely with custom design engineers, and cross-functional teams at the silicon and module levels.

• BS and a minimum of 10 years relevant industry experience.
• Solid understanding of timing analysis concepts such as setup/hold time calculation, POCV on timing paths, timing constraints, transistor-level delay characterization, rise/fall time balancing, etc.
• Experience of timing analysis and verification in high-speed design such as Ser Des and ADC.
• In-depth knowledge and analytical understanding of mixed-signal design techniques.
• Strong track record of delivering silicon IPs with design and verification.
• Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.

• Master’s Degree with 8+ years of relevant industry experience.
• Experience with STA tools such as Nano Time, Prime Time, or Tempus.
• Experience in analog/mixed-signal circuit design from architecture to fundamental implementation.
• Experience in SRAM design.
• Experience in timing / SDC constraints generation and management.
• Good understanding of tool algorithms for noise glitch, cross-talk delay, and margining with POCV.
• Proficiency in scripting languages (Python, Tcl or Perl).