SerDes Characterization Lead, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
• 8 years of experience in high-speed Ser Des characterization, silicon and system validation, or electrical physical layer (PHY) design.
• 5 years of experience in technical leadership driving silicon or hardware characterization programs.
• Experience participating in or contributing to industry standards bodies (e.g., IEEE, OIF, PCI-SIG, or similar).

• PhD in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
• Experience architecting automated, high throughput characterization laboratories and test methodologies.
• Experience in cross-functional and external leadership, establishing relationships across test and measurement vendors, PHY IP suppliers, and standard committees.
• Subject matter expertise in electrical/optical interconnects, DSP-based Ser Des architectures, and advanced channel modeling.
• Experience in technical vision, and executive communication skills.

Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concepts all the way through to high-volume manufacturing.

Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $236000 - $329000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.

• Serve as the technical lead and owner for high-speed Serializer/Deserializer (Ser Des) IP, silicon, and system characterization across next-generation data center and AI/ML accelerator platforms.
• Define comprehensive Ser Des characterization strategies, test methodologies, equipment procurement, and lab automation infrastructure from early silicon bring-up to production readiness.
• Represent the organization in industry standard bodies (e.g., IEEE 802.3, OIF-CEI) and drive the adoption of emerging electrical and optical interconnect technologies.
• Partner cross-functionally with Silicon Architecture, ASIC Design, Signal/Power Integrity, System hardware, and Packaging teams to correlate lab measurements with simulations and influence future architecture. Interface with external silicon vendors, IP providers, and test equipment manufacturers to drive ecosystem roadmaps aligned with future infrastructure requirements.
• Drive next generation interconnect technology pathfinding, vendor engagement, and prototyping efforts. Mentor, guide, and technically lead a team of Ser Des characterization engineers.