Senior Methodologist AIML Enhanced Design​/Verification

Senior Methodologist for AIML Enhanced Design/Verification This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.

Our culture thrives onfinding new and better ways to accelerate what’s next.

We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.

We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.

Open up opportunities with HPE.

Job Description:

We are seeking a
Senior AIML enhanced
Design/Verification Methodology Engineer
to join our team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs
using AIML enhanced methodologies
. You will architect, build, and maintain
AIML enhanced or agentic solutions for design and verification environments
with applications to all phases of design and verification closure. You will collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout. This is a high-impact position for someone who thrives on solving intricate design/verification challenges using AIML methodologies.

• Use both “classical” and Generative-AI methodologies to architect, develop, and maintain agents, skills, and other AI based design and verification infra-structures. The ideal person will have balanced knowledge of chip design and AIML methodologies to contribute meaningfully to the creation of architecture, design, verification, and physical design assets. These includes but not limited to:
• Creating UVM-based testbench environments from ground up or enhance the existing ones using AI. Creating verification plans with clear coverage goals and closure criteria. Performing root cause analysis of failures and work with design teams to drive resolution.
• Automating generation of RTL from spec.
• Evaluation of industry tools.

• Bachelor's degree
  in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent).
• 3
  -5 years of direct hands-on experience with
  AIML methods, concepts and workflows
  — including experience in creating agents, skills, APIs, model, etc. for Design/Verification problem.
• 5 - 7 years of experience in production development of RTL design and verification infrastructure.Strong experience in
  System Verilog
  for design or verification.
• Solid understanding of digital design fundamentals (RTL, timing, synthesis constraints).
• Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Effective communication and collaboration skills in cross-functional team settings.

• Master's or Ph.D.in Electrical Engineering or Computer Science.
• Experience with
  formal verification
  tools and techniques (e.g., Jasper Gold, VC Formal) is a plus.
  
  Experience with
  emulation and FPGA prototyping
  platforms (e.g., Palladium, Protium, Veloce) is also a plus.
• Industry conference/peer reviewed journal publications in the design/verification methodology development and/or
  AIML
  .

You'll work on challenging, cutting-edge designs alongside a talented engineering team that values innovation, quality, and continuous learning. We offer competitive compensation, comprehensive benefits, and opportunities for professional growth.

Accessibility

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