TPU PCIe Design Lead & RTL Architect
Listed on 2026-10-06
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Engineering
Hardware Engineer, Architect / Sr. Architect, Electronics Engineer -
Design & Architecture
Architect / Sr. Architect
Google Inc. Sunnyvale is seeking an experienced PCIe Design Engineer to shape the future of AI/ML hardware acceleration, focusing on TPU architecture and integration.
You will design and verify SoC-level RTL for next-gen data center accelerators, building clocking, reset, error handling, and power management.
Join a collaborative team advancing Google's TPUs, driving silicon bring-up and performance for AI infrastructure.
For the TPU PCIe Design Lead & RTL Architect position at Google Inc., we are reviewing applications now.
This role, TPU PCIe Design Lead & RTL Architect at Google Inc., could be your next opportunity.
Are you ready to take on the TPU PCIe Design Lead & RTL Architect role at Google Inc.?
We would love to welcome a new TPU PCIe Design Lead & RTL Architect to our team in Sunnyvale, CA, United States.
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