More jobs:
TPU RTL Design Engineer: -Speed Interconnects
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-06-21
Listing for:
Google Inc.
Full Time
position Listed on 2026-06-21
Job specializations:
-
IT/Tech
Systems Engineer
Job Description & How to Apply Below
Google Inc. is seeking a High-Performance ASIC Designer in Sunnyvale, CA. The role involves designing RTL IP for AI and networking accelerators, working closely with various teams to ensure integration and performance.
Candidates should possess a Bachelor's degree and at least 4 years of ASIC design experience, along with a deep knowledge of digital systems and high-speed interconnects. Competitive compensation includes a salary range of $138,000 – $198,000 plus bonuses and equity.
#J-18808-LjbffrTo View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×