R&D Architect-18137

R&D Architect

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You are a highly skilled and experienced software engineer with a solid background in development and routing algorithm tools. You thrive in dynamic, collaborative environments and possess a strong understanding of modern object-oriented C++ coding techniques. Your deep understanding of graph theory and its applications allows you to solve real-world challenges in multiple die design and manufacturing. You are not just a coder;

you are a thinker and a doer, capable of contributing to the development of cutting-edge routing tools. Your ability to troubleshoot, debug, and offer support to application engineers and users makes you a valuable team player. You are ready to take on the challenge of contributing to code refactoring efforts for legacy modules, aiming to increase efficiency and re-usability. Your communication skills allow you to effectively collaborate with an internationally distributed team of R&D and application engineers, and you are committed to continuous learning and professional growth.

• Design and develop advanced interposer routing algorithms for multi-die systems, including signal routing, power/ground distribution, and shielding strategies
• Implement and optimize routing engines using modern C++ (C++14/17/20), focusing on performance, memory efficiency, and maintainability
• Apply graph theory and computational geometry to model and solve complex routing constraints in 2.5D and 3D chip architectures
• Refactor and modernize legacy routing modules to improve code reusability, reduce technical debt, and enable future feature development
• Debug and resolve complex algorithmic and performance issues reported by application engineers and customer deployments
• Collaborate with a globally distributed R&D team across the US, India, and Asia to align on architecture, API design, and release milestones
• Provide technical guidance and code reviews to other engineers, helping elevate the quality and consistency of the routing platform

• Enable Synopsys customers to route increasingly complex multi-die and chiplet-based designs that would otherwise be infeasible
• Improve runtime and memory performance of interposer routing tools, directly reducing turnaround time for design teams
• Increase code maintainability and extensibility of core routing modules, making future feature development faster and safer
• Reduce support escalations by building more robust, predictable routing behavior that handles edge cases gracefully
• Influence the technical direction of the routing platform through architecture proposals, design reviews, and cross-team collaboration
• Mentor engineers on the team, raising the bar for algorithm design, C++ best practices, and debugging methodology
• Contribute to Synopsys' leadership in advanced packaging and multi-die design, a critical area as the industry moves beyond monolithic chips

• 12+ years of software development experience building production-quality tools, preferably in EDA, CAD, or computational geometry domains
• Expert-level proficiency in modern C++ (C++14 or later), including STL, templates, memory management, and performance optimization
• Strong foundation in graph algorithms, data structures, and algorithmic complexity analysis, with demonstrated ability to apply them to real-world problems
• Experience designing, implementing, and debugging complex algorithms in large codebases with multiple contributors
• MS or PhD in Computer Science, Electrical Engineering, or a related technical field
• Hands-on experience with routing, placement, or other physical design algorithms is a strong plus
• Familiarity with EDA tools, VLSI design flows, or semiconductor manufacturing concepts is a plus

• You can take a vague feature request from a product manager or customer and turn it into a clear technical plan with milestones, risks, and tradeoffs
• You write code that other engineers can understand six months later, even when the problem is inherently complex
• When a customer-reported bug lands in your queue, you do not just fix the symptom, you trace it back to the root cause and prevent the class of issue from recurring
• You are comfortable presenting technical work to a mixed audience, whether it is a design review with senior architects or a walkthrough with application engineers who need to support your feature
• You push back when a proposed solution does not scale or when a design decision will create maintenance problems down the road, and you do it constructively
• You stay current with developments in C++, algorithms, and EDA…