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Senior Design Verification Architect; ASIC/FPGA & UVM
Job in
Tempe, Maricopa County, Arizona, 85285, USA
Listed on 2026-07-25
Listing for:
Viasat
Full Time
position Listed on 2026-07-25
Job specializations:
-
Engineering
Systems Engineer, Test Engineer
Job Description & How to Apply Below
Viasat is seeking a Design Verification Engineer to join a talented team that develops cutting-edge communications technology for ASICs and FPGAs. You will architect verification environments, build test benches, and drive coverage closure with RTL, System and software engineers.
The role emphasizes hands-on debugging, testplan creation, regression management, and tool evaluation in a fast-paced, Agile Jira-driven environment. US citizenship and ability to travel up to 10% are required.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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