Memory Design Verification Engineer; SystemVerilog/UVM
Job in
Dresden, Weakley County, Tennessee, 38225, USA
Listed on 2026-05-16
Listing for:
Ferroelectric-Memory-Gmbh-2
Full Time
position Listed on 2026-05-16
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Engineering Design & Technologists, Test Engineer
Job Description & How to Apply Below
Location: Dresden
Ferroelectric-Memory-Gmbh-2 is seeking a Design Verification Engineer to join their team in Dresden, Tennessee. The ideal candidate should have a Master’s degree in Electrical or Computer Engineering and over 5 years of experience in ASIC/DRAM/NAND/NOR Memory design verification. Proficiency in System Verilog and UVM methodology is essential, along with knowledge of Cadence verification tools. The role includes developing UVM-based verification environments and collaborating with design engineers to ensure performance and reliability of designs.
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