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Senior Memory Design Verification Engineer; SystemVerilog​/UVM

Job in Dresden, Weakley County, Tennessee, 38225, USA
Listing for: Ferroelectric-Memory-Gmbh-2
Full Time position
Listed on 2026-07-11
Job specializations:
  • Engineering
    Test Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 160000 USD Yearly USD 120000.00 160000.00 YEAR
Job Description & How to Apply Below
Position: Senior Memory Design Verification Engineer (SystemVerilog/UVM)
Location: Dresden

Ferroelectric-Memory-Gmbh-2 is seeking a Design Verification Engineer with expertise in System Verilog and UVM to verify memory designs and collaborate with architects and designers to meet performance and reliability requirements. The role focuses on mixed-signal verification and memory interfaces in a fast-paced environment.

You will develop UVM-based verification environments, create test benches, stimuli, and memory models, and perform DDR4/DDR5 verification at block and system levels using

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Position Requirements
10+ Years work experience
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