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Senior Memory Design Verification Engineer; SystemVerilog/UVM
Job in
Dresden, Weakley County, Tennessee, 38225, USA
Listed on 2026-07-11
Listing for:
Ferroelectric-Memory-Gmbh-2
Full Time
position Listed on 2026-07-11
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Location: Dresden
Ferroelectric-Memory-Gmbh-2 is seeking a Design Verification Engineer with expertise in System Verilog and UVM to verify memory designs and collaborate with architects and designers to meet performance and reliability requirements. The role focuses on mixed-signal verification and memory interfaces in a fast-paced environment.
You will develop UVM-based verification environments, create test benches, stimuli, and memory models, and perform DDR4/DDR5 verification at block and system levels using
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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