Senior Electrical Engineers - FPGA Design - Actively Our Engineering Teams

Location: US-MA-TEWKSBURY-TB1 ~ 50 Apple Hill Dr ~ ASSABET BLDG

Date Posted:

Country: United States of America

Position Role Type: Onsite

U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance

Security Clearance Type: Secret - Current

Security Clearance Status: Active and existing security clearance required after day 1

• Design and deliver production quality FPGA releases from initial proof of concept up to production
• Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
• Translate system level requirements into FPGA requirements
• Design and code in VHDL for reliability and maintainability
• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
• Help drive projects and execute program schedules on time and budget
• Create complete documentation including requirements, verification plan, and user’s guides
• Lead small teams and mentor junior engineers
• Support internal and external technical reviews

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience
• A minimum of 5 years of experience to include one of the following:
• FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
• Xilinx or Microsemi devices and flow tools
• Delivering FPGA/ASIC solutions to system level applications
• Experience with integration and debug of FPGA/ASIC devices

• FPGA/ASIC design experience in one or more of the following areas:
• Radar processing techniques
• Image processing techniques for visual and infrared sensors
• Embedded systems design using ARM, Microblaze, or Nios processors
• Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
• Constrained random verification in UVM using System Verilog
• Verification utilizing emulation platforms, such as Veloce

• Salary range: 86,800 USD - 165,200 USD (subject to experience and qualifications)
• Relocation assistance may be provided
• Work schedule:
  
  9/8 Schedule – every other Friday off
• Medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays
• Annual short‑term and/or long‑term incentive compensation programs may be available depending on position level and collective‑bargaining agreement

Eligibility & Equal Opportunity: RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected class. RTX provides affirmative action and complies with applicable regulations.