Principal Electrical Engineer-FPGA Verification

Date Posted:

Location:

Tewksbury, MA or Marlborough, MA. Address: 50 Apple Hill Dr, Assistant Building.

Position Type:
Onsite. Citizenship: U.S. citizen required for security clearance. Security Clearance:
DoD Secret, active and existing required after day 1.

The Radar Digital Products (RDP) Department at Raytheon is seeking an experienced Principal-level Electrical Engineer to verify FPGA‑based designs for control and/or signal processing radar applications.

• Own or contribute to the successful completion of FPGA‑based designs, on time and on budget.
• Verify designs utilizing self‑checking techniques with directed and constrained random tests, while tracking functional and code coverage using UVM.
• Create complete verification documentation including verification plan and report.
• Demonstrate self‑motivation, with little supervision required.
• Work cooperatively with systems, hardware, software engineers, and program management to ensure product success.
• Support internal and external technical reviews.

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience in digital design verification.
• Strong proficiency in System Verilog for both design and verification (interfaces, clocking blocks, assertions).
• Hands‑on experience building UVM‑based test benches from scratch, including environment, agent, scoreboard, and coverage components.
• Solid understanding of constrained‑random verification and functional coverage methodology.
• Familiarity with AXI, PCIe, Ethernet, DDR protocols.
• Experience with industry‑standard simulators (e.g., Questa, VCS, Xcelium).
• Experience with regression management and debugging of complex, intermittent failures.
• Ability to develop and maintain verification plans tied to design specifications and coverage closure criteria.
• Experience with version control systems (e.g., Git, Clear Case, SVN) in a team‑based development environment.
• Proficiency with Git, branching strategies, pull requests, and collaborative workflows.
• Experience with UVMF (UVM Framework) for structured, reusable testbench development.
• Familiarity with Vivado and Quartus FPGA simulation flows.
• Experience with scripting languages (Python, Tcl, Perl) for test automation and tooling.
• Experience designing FPGAs using VHDL.
• Familiarity with SLURM workload manager for job scheduling and compute cluster resource management.
• Prior experience mentoring junior verification engineers.
• Existing DoD security clearance.

• Salary range: 107,500 USD – 204,500 USD.
• Health insurance (medical, dental, vision).
• Life insurance, short‑term disability, long‑term disability.
• 401(k) match.
• Flexible spending accounts.
• Flexible work schedules.
• Employee assistance program.
• Employee Scholar Program.
• Parental leave.
• Paid time off and holidays.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class.