Principal FEOL​/MOL integration Engineer

Principal FEOL/MOL Integration Engineer

Location:

Albany, TX

As a Principal Process Integration Engineer within our FEOL/Middle-of-Line process integration organization, you will operate as a senior individual contributor and technical authority for the team. This is a fab-facing role: you will define and stand up new process integration routes, build out electrical test (e-test) capability from the ground up, and serve as the principal technical owner for cross-business-unit (X-BU) programs that bring TEL's tool and process portfolio together on internal test vehicles.

You will work closely with TEL's onsite business units (BUs), factories, and ecosystem partners to verify and integrate processes that demonstrate the benefits of TEL technologies for advanced logic and memory devices. Success in this role means owning route architecture end to end — from flow definition through wafer execution, electrical characterization, and data-driven decision-making — and setting the technical standard for the engineers around you.

Responsibilities:

• Serve as the principal technical authority for FEOL/MOL integration, driving direction, priorities, and technical quality through hands-on execution and mentorship as a senior individual contributor (no direct reports).
• Define and build new process integration routes across litho, etch, films, wets, and CMP for FEOL/MOL test vehicles, including flow definition, mask/reticle planning, and split strategy.
• Establish and own e-test (electrical test) capability for the team: parametric test structure and PCM design, test chip planning, probe card / test program coordination, wafer-level parametric extraction, and correlation of electrical results back to unit process and integration knobs.
• Lead cross-business-unit (X-BU) projects, coordinating roadmaps, tool capabilities, and deliverables across TEL BUs, factories, and onsite partners to meet current and future customer needs through standard and novel integration flows.
• Design, execute, and demonstrate proposed integration solutions on TEL internal vehicles, including statistical analysis of results.
• Own lot management including process splits, DOEs, metrology setup, and data analysis/evaluation.
• Support internal and external stakeholders in resolving integration and process issues through current and future TEL equipment capability.
• Maintain rigorous quality-control, documentation, and data-integrity practices, and set those standards for the team.

Required & Preferred

Skills:

• Demonstrated FEOL/MOL process integration experience with a strong track record of building new processing routes from flow definition through wafer execution. (Required)
• Hands-on electrical test / parametric test experience — test structure design and interpretation (e.g., MOSCAP, TLM, Kelvin, Van der Pauw, BEOL daisy chains), PCM/wafer-level para metrics, and probe/test-program coordination. (Strongly preferred / required for the e-test build-out)
• Experience leading cross-functional or cross-BU technical projects, including planning and scheduling. (Required)
• Lot management skills using SIVIEW MM/SM. (Preferred)
• Metrology and analysis tool operation, including inline CDSEM and cross-sectional SEM. (Required)
• Knowledge of experiment design (DOE) and techniques for tool and process optimization. (Required)
• EUV lithography and/or 193i immersion experience. (Preferred)
• Strong data-analysis skills; experience with JMP or equivalent statistical software, Excel, and measurement/analysis software (e.g., Quartz PCI). (Preferred)
• Excellent verbal and written communication, including technical presentations. (Required)
• Strong self-management, teamwork, collaboration, and problem-solving skills. (Required)
• Proficiency with personal computer, peripherals, and standard software (MS Windows, MS Office, networking). (Required)

Typical

Education and Experience:

• Master's degree in a related science/engineering field — preferably Electrical Engineering, Materials Science/Engineering, Chemical Engineering, Mechanical Engineering, Chemistry, or Physics — with a minimum of 8 years of related semiconductor-industry engineering experience; or PhD with a minimum of 5 years' experience;…