Principal Design Engineer

We are currently seeking a highly motivated and experienced Analog / Power IC Design Engineer to lead the architecture, design, and silicon execution of next‑generation power management ICs. This is a hands‑on technical role with end‑to‑end ownership, from initial concept through to production, working closely with systems, device, layout, and validation teams. It’s a key position for someone who has successfully brought power ICs into high‑volume production and is interested in shaping future architectures.

• Lead the architecture, design, and verification of power management ICs, from transistor‑level blocks to full‑chip integration
• Define and evaluate system‑level trade‑offs for next‑generation power supplies in collaboration with applications and systems teams
• Drive IC architecture decisions across AC‑DC, DC‑DC, ACF, LLC, QR, and related power topologies
• Collaborate with device, modeling, and EDA teams to optimize simulation methodologies and device selection
• Guide layout and floor planning to ensure performance, reliability, and manufacturability
• Own tape‑out execution and ensure delivery against performance, schedule, and quality targets
• Lead silicon bring‑up, validation, debugging, and correlation with simulations
• Support yield improvement, failure analysis, and production release
• Mentor junior engineers and contribute to design best practices

• Proven experience as a chip lead or technical owner on at least one successful silicon program
• Strong track record delivering power ICs from concept through high‑volume production
• Expertise in AC‑DC and/or DC‑DC power IC design
• Deep knowledge of analog and mixed‑signal building blocks (bandgaps, LDOs, comparators, charge pumps, op‑amps)
• Strong understanding of semiconductor device physics, power transistors, and silicon fabrication processes
• Excellent communication skills and a collaborative, self‑driven mindset

• MSEE with 7+ years or PhD with 5+ years in analog/mixed‑signal IC design
• Proficiency with EDA tools such as Cadence Virtuoso/Spectre, post‑layout simulation, Monte Carlo, and corner analysis
• Experience with DFT methodologies, characterization strategies, and production test planning
• Hands‑on lab experience with silicon validation and debug