Technical Project Manager, Semiconductor

Technical Project Manager, Semiconductor About Us

Red Cell Partners is an incubation firm building and investing in rapidly scalable technology-led companies that are bringing revolutionary advancements to market in three distinct practice areas: healthcare, cyber, and national security. United by a shared sense of duty and deep belief in the power of innovation, Red Cell is developing powerful tools and solutions to address our Nation’s most pressing problems.

Technical Project Manager - Semiconductor

About Claros

Claros innovates at the intersection of power and compute. We build advanced semiconductor power management solutions that improve AI compute capacity, efficiency and reliability. Claros is an early-stage startup company located in Torrance, CA. If you are looking for challenging work and a strong technical environment with the collaborative & supportive culture, then Claros Tech is the company for you. We offer industry the best competitive pay & benefits and early-stage stock options.

Location: Minimum of 3 days a week in the office in Torrance, CA. (Hybrid role)

This role will report to: CTO/CEO

About the Team

We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking. Our response is never “no, but….” instead “yes, if….”. We are mindful of our personal and organizational blinders and try to build an environment where our team members are At Their Best.

About The Role

We are seeking a Technical Project Manager to deliver chips, advanced modules, and licensable IP from design handoff through mass production. This role combines semiconductor process and packaging expertise with cross-functional execution, vendor management, and customer engagement. The ideal candidate functions in a hybrid role for both customer and internal facing. Customer facing is a blend of product, application, and product management to ensure customer satisfaction and long-term partnership.

Internally, bringing advancements in semiconductor, packaging, testing, and manufacturing while guiding engineering decisions together with product architecture.

• The ideal candidate is highly organized, proactive, and articulate, with the technical credibility to partner directly with customer engineering teams working on the most advanced xPU SoCs in the industry. This role offers significant opportunity for impact, ownership, and growth, contributing directly to both customer product success and Power Lattice’s commercial momentum.
• Serve as the primary technical and strategic interface for key AI, Data Center and server customers, understanding their architecture roadmaps, KPIs, and deployment models. Making sure the internal engineering team is aligned with the customer’s expectations.
• Drive end-to-end product execution for chips, advanced 2.5D/3D modules, and licensable IP, ensuring on-time, on-spec, and on-cost delivery.
• Act as the central point of coordination across design, validation, manufacturing, and supply chain to ensure cross-functional alignment and execution against customer milestones.
• Lead development of reusable IP blocks for internal and external licensing.
• Executing integration of advanced process nodes and packaging techniques (chiplets, 3D).
• Evaluate, qualify, and manage vendors alongside our internal subject matter experts; negotiate pricing and creative financial agreements to optimize cost and risk.
• Distill complex technical issues into clear, simple terms and present solution paths with trade-offs.

• BSEE required; MSEE or PhD preferred.
• 8+ years in semiconductor product development with high-volume delivery of chips, modules, and IP.
• Hybrid Skillset:
  Demonstrated ability to operate across product engineering, application engineering, and product management disciplines
• Experience taking devices through qualification, i.e. Automotive standards (AEC-Q100, ISO 26262).
• Strong knowledge of semiconductor process technology, advanced packaging, and DFM/DFT flows.
• Familiarity with phase-gate and structured project management processes.
• Demonstrated ability to reduce overall product cost…