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FPGA Engineering Manager - Memory Test & RTL Lead
Job in
Tualatin, Washington County, Oregon, 97062, USA
Listed on 2026-07-16
Listing for:
Teradyne
Full Time
position Listed on 2026-07-16
Job specializations:
-
Engineering
Hardware Engineer
Job Description & How to Apply Below
Teradyne's Memory Test Division in Tualatin, OR is seeking an experienced FPGA Engineering Manager to lead a small team and deliver advanced memory test solutions, combining digital and analog design with PCIe, DDR, and SERDES interfaces.
You will plan multiple FPGA projects, mentor 4–6 engineers, collaborate across hardware, software, and firmware, and drive architectural reviews, RTL coding, and lab validation to ensure on-time delivery.
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