Senior FPGA Design Engineer - Memory Test & RTL Architect
Job in
Tualatin, Washington County, Oregon, 97062, USA
Listed on 2026-07-16
Listing for:
Teradyne
Full Time
position Listed on 2026-07-16
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer, Hardware Engineer, Systems Engineer
Job Description & How to Apply Below
Teradyne’s Memory Test Division seeks an FPGA Engineer to develop next‑generation memory test solutions. You will architect FPGA designs for Flash and DRAM test instrumentation, guide junior engineers, and convert complex customer requirements into robust, extensible implementations.
Ideal candidates have 8+ years in FPGA design, strong RTL/Verilog skills, and experience with FPGA tool flows and lab validation. Occasional travel may be required.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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