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Lead FPGA Architect Memory Test Systems

Job in Tualatin, Washington County, Oregon, 97062, USA
Listing for: Teradyne
Full Time position
Listed on 2026-07-18
Job specializations:
  • Engineering
    Systems Engineer, Test Engineer, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 154900 - 247800 USD Yearly USD 154900.00 247800.00 YEAR
Job Description & How to Apply Below
Position: Lead FPGA Architect for Memory Test Systems

Teradyne is seeking an FPGA Engineer to develop next‑generation memory test solutions. You will architect FPGA designs for Flash and DRAM instruments and provide technical guidance to junior engineers, shaping reliable, extensible test systems.

You will transform customer requirements into robust designs, maintain existing FPGA platforms, and contribute to schedule commitments while occasionally traveling to meet project goals.

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