Senior FPGA Design Engineer; Memory Test, Tualatin

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions helps manufacturers develop and deliver products quickly, efficiently, and cost-effectively.

Location:

Tualatin, OR, US;
San Jose, CA, US

Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions. You will architect and implement FPGA solutions to support next-generation Flash and DRAM test instrumentation, and provide technical guidance to junior engineers.

• Architect and implement FPGA solutions for next‑generation Flash and DRAM test instrumentation.
• Provide technical guidance to junior engineers.
• Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
• Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
• Maintain schedule commitments and deliver high‑quality end products.
• Occasional travel may be required.

We seek individuals who share our passion for customer success and innovation. If you’re ready to join us in this mission, review the minimum criteria for the position.

• B.S. or M.S. in Electrical Engineering or a closely related discipline and 8+ years of relevant work experience.
• Experience with Digital Design and Architecture.
• RTL coding, synthesis, timing closure, and lab validation.
• Experience with Static Timing Analysis of ASICs or FPGAs.
• Experience with digital simulation testbench creation.
• Experience with C or C++.
• Familiarity with lab equipment such as oscilloscopes, power supplies, and waveform generators.

• FPGA Transceiver‑based design experience.
• Experience with DRAM and Flash Memory interfaces.
• Experience with Intel/Xilinx FPGA tool flows.
• Proficiency with Verilog HDL language.
• Familiarity with UVM methodology.
• Linux and Windows operating systems experience.
• Familiarity with ATE instrumentation.

The base salary range for this role is $154,900–$247,800. This range is a good‑faith estimate; the actual amount will correspond to experience and skill set and may fluctuate based on demand and location.

This position is eligible for discretionary bonus(es) based on financial performance.

Teradyne offers a variety of robust health and well‑being benefit programs, including medical, dental, vision, flexible spending accounts, retirement savings plans, life and disability insurance, paid vacation and holidays, tuition assistance programs, and more.

Teradyne is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected veteran status.