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Senior FPGA Design Engineer - Memory Test Systems
Job in
Tualatin, Washington County, Oregon, 97062, USA
Listed on 2026-07-18
Listing for:
Teradyne
Full Time
position Listed on 2026-07-18
Job specializations:
-
Engineering
Electronics Engineer, Test Engineer, Hardware Engineer
Job Description & How to Apply Below
Teradyne’s Memory Test Division (MTD) is seeking an FPGA Design Engineer to develop next generation Flash and DRAM test instrumentation. You will work on architectural and RTL‑level design, collaborating with a global team to translate customer needs into reliable FPGA solutions.
Ideal candidates have a BS in Electrical Engineering or related field with 5+ years of experience or an MS with 3+ years, strong Verilog/C/C++, timing analysis, and lab‑equipment familiarity.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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