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Digital Verification Lead — FPGA & SystemVerilog

Job in Tualatin, Washington County, Oregon, 97062, USA
Listing for: Teradyne
Full Time position
Listed on 2026-07-21
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 154900 - 247800 USD Yearly USD 154900.00 247800.00 YEAR
Job Description & How to Apply Below

Teradyne is seeking a digital functional verification technical lead to plan, strategize, and execute challenging FPGA verification projects. You will provide technical leadership for large, cross-site teams and collaborate with hardware, software, and applications groups.

The role requires deep experience with System Verilog, UVM, verification planning, and regression analysis. You will mentor engineers across time zones and contribute to reusable verification IPs.

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