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Senior FPGA Design Engineer — Memory Test Innovation
Job in
Tualatin, Washington County, Oregon, 97062, USA
Listed on 2026-07-21
Listing for:
Teradyne
Full Time
position Listed on 2026-07-21
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
Teradyne’s Memory Test Division (MTD) is seeking an FPGA Engineer to advance memory test solutions, blending advanced digital/analog design with cutting‑edge ASIC/FPGA tech and hands‑on lab work.
You will architect FPGA solutions for Flash/DRAM test instrumentation, guide junior engineers, and translate concepts into reliable, extensible designs while maintaining project timelines. Occasional travel may be required; bases in Tualatin, OR and San Jose, CA.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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