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Senior FPGA Design Engineer; MTD, Tualatin

Job in Tualatin, Washington County, Oregon, 97062, USA
Listing for: Teradyne
Full Time position
Listed on 2026-07-21
Job specializations:
  • Engineering
    Test Engineer, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 154900 - 247800 USD Yearly USD 154900.00 247800.00 YEAR
Job Description & How to Apply Below
Position: Senior FPGA Design Engineer (MTD, Tualatin, OR)

Location: Tualatin, OR;
San Jose, CA, US

Opportunity Overview

Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting‑edge memory test solutions. MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world’s most advanced memory technologies, combining state‑of‑the‑art digital and analog designs, cutting‑edge ASIC/FPGA technologies, liquid cooling, and high‑performance signal delivery.

Responsibilities
  • Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
  • Provide technical guidance to junior engineers.
  • Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
  • Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
  • Maintain schedule commitments and deliver high quality end products.
  • Occasional travel may be required.
Qualifications
  • B.S. or M.S. in Electrical Engineering or closely related discipline and 8+ years of relevant work experience.
  • Experience with Digital Design and Architecture.
  • RTL coding, synthesis, timing closure and lab validation.
  • Experience with Static Timing Analysis of ASICs or FPGAs.
  • Experience with digital simulation testbench creation.
  • Experience with C or C++.
  • Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.
Desired Skills
  • FPGA Transceiver based design experience.
  • Experience with DRAM and Flash Memory interfaces.
  • Experience with Intel/Xilinx FPGA tool flows.
  • Proficiency with Verilog HDL Language.
  • Familiarity with UVM Methodology.
  • Linux and Windows operating systems experience.
  • Familiarity with ATE instrumentation.
Compensation

The base salary range for this role is $154,900–$247,800. This range is a good faith estimate and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

Job Segment

Design Engineer, Instrumentation, Electrical Engineering, Manufacturing Engineer, HVAC, Engineering, Operations

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Position Requirements
10+ Years work experience
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