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Senior FPGA Design Engineer — Memory Test Systems
Job in
Tualatin, Washington County, Oregon, 97062, USA
Listed on 2026-09-05
Listing for:
Teradyne
Full Time
position Listed on 2026-09-05
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Job Description & How to Apply Below
Teradyne’s Memory Test Division (MTD) seeks an FPGA Design Engineer to support cutting-edge memory test solutions. You will architect FPGA designs, guide junior engineers, and translate customer requirements into robust, scalable implementations.
The role demands strong digital design, Verilog, and FPGA tool-flow expertise, with occasional travel and a focus on delivering reliable, high-quality instruments.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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