Data Fabric Verification Engineer

Responsibilities

• Architected and developed complex verification environments in System Verilog, including scripting using Perl, Ruby, Make, or the likes.
• Exposure to RTL design, software development, formal verification, or other related domains.
• Good understanding of computer organization/architecture.
• Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics

• Bachelors or Master’s degree in computer engineering/Electrical Engineering preferred

Pre-silicon Validation, System Verilog.

5-8 Years

The expected compensation for this role ranges from $60,000 to $148,500. Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience.

Eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.

Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.