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Pre-Silicon Verification Engineer - SystemVerilog

Job in Santa Clara, Washington County, Utah, 84765, USA
Listing for: Wipro
Full Time position
Listed on 2026-08-22
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 60000 - 148500 USD Yearly USD 60000.00 148500.00 YEAR
Job Description & How to Apply Below
Location: Santa Clara

A global technology consulting firm seeks a candidate to architect and develop complex verification environments using System Verilog. The role requires 5-8 years of experience, exposing candidates to RTL design and formal verification tools like VCS, Cadence, and Mentor Graphics. This position offers a salary range of $60,000 to $148,500, depending on various factors, and includes full medical and dental benefits, disability insurance, and paid time off.
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