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Quantum Bump Integration Engineer
Job in
Essex Junction, Chittenden County, Vermont, 05453, USA
Listed on 2026-06-02
Listing for:
GLOBALFOUNDRIES US Inc.
Full Time
position Listed on 2026-06-02
Job specializations:
-
Engineering
Electrical Engineering, Systems Engineer
Job Description & How to Apply Below
Job Summary
Global Foundries Fab9 is seeking a highly skilled and motivated R&D bump process engineer for the Quantum Advanced Packaging team. The role focuses on driving next‑generation interconnect scaling in the Advanced Packaging and Photonics Center (APPC) and with partners. Primary responsibility is to own development and integration of cryogenic, superconducting bumping processes enabling scalable quantum hardware packaging.
Essential Responsibilities- Lead development of cryogenic‑compatible bump interconnect technologies (e.g., indium, SnAg, Cu pillar, superconducting metals).
- Define and optimize bump structures, metallurgy, and process flows for superconducting integration.
- Establish process windows that ensure electrical, thermal, and mechanical stability at mK–K temperatures (CTE mismatch, fatigue, diffusion).
- Own end‑to‑end bump integration flows from wafer‑level processing through assembly and qualification.
- Develop and implement integration schemes across 2.5D/3D architectures (interposers, TSVs, die‑to‑wafer flows).
- Drive alignment between unit processes (plating, lithography, CMP, bonding) and system‑level packaging requirements.
- Enable rapid prototyping to ensure smooth movement of development lots.
- Support transition from R&D to pilot/high‑volume manufacturing, ensuring process robustness.
- Develop integration strategies to improve yield, reduce defectivity, and enhance manufacturability.
- Identify and analyze failure modes (e.g., delamination, interconnect resistance shifts, cryo‑induced stress).
- Apply DOE, statistical analysis, and root‑cause methodologies to drive continuous improvement.
- Collaborate with test teams to characterize interconnect behavior at cryogenic temperatures (DC, RF/microwave).
- Ensure bump/interconnect design supports low‑loss signal delivery, minimal thermal leakage, and reduced crosstalk and noise critical for qubit coherence.
- Partner with device/qubit engineers, cryogenic system teams, packaging & assembly teams, and modeling and reliability teams.
- Interface with vendors, tool suppliers, and OSAT partners for process development and scale‑up.
- Drive next‑generation bump scaling (pitch, height, material systems) aligned with quantum system scaling needs.
- Contribute to advanced packaging roadmap (e.g., high‑density I/O, superconducting interposers).
- Scout and evaluate new materials, processes, and integration concepts.
- Work with design teams to translate system requirements into bump/interconnect specs (pitch, impedance, current limits).
- Support co‑design of package + qubit + control electronics integration to reduce wiring bottlenecks and thermal load.
- Generate process documentation, specs, and integration guidelines.
- Deliver technical reports and updates to internal/external stakeholders.
- Support IP generation (invention disclosures, publications, conference contributions).
- Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
- Take part in hiring of other Advanced Packaging team members.
- Mentor and guide new hires to assume their roles and responsibilities.
- Other duties as assigned by manager.
- Master’s degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science or related field from an accredited institution.
- MS degree with at least 8 years of prior related work experience.
- In‑depth knowledge of BEOL processes and integration, bump/wafer finish integration, wafer test/probe, OSAT collaboration, and package development & assembly.
- Strong problem‑solving and technical troubleshooting skills including expertise in design of experiments.
- Must have at least an overall 3.0 GPA and proven good academic standing.
- Fluency in English (written & verbal).
- Travel up to 10%.
- PhD education level preferred with at least 5 years of prior related work experience.
- Demonstrated prior leadership experience in the workplace, school projects, competitions, etc.
- Project management skills, i.e., the ability to innovate and execute on solutions that matter; the ability to navigate ambiguity.
- Strong written and verbal…
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