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Quantum Assembly Engineer

Job in Essex Junction, Chittenden County, Vermont, 05453, USA
Listing for: GLOBALFOUNDRIES US Inc.
Full Time position
Listed on 2026-06-02
Job specializations:
  • Engineering
    Electrical Engineering, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 118000 - 210000 USD Yearly USD 118000.00 210000.00 YEAR
Job Description & How to Apply Below
Location: Essex Junction

Global Foundries Fab9 is seeking a highly skilled and motivated R&D assembly engineer to become part of our Quantum Advanced Packaging team. This role will entail driving next-generation assembly scaling development efforts in our Advanced Packaging and Photonics Center (APPC) as well as with our partners. The primary responsibility of this position is to own development and integration of cryogenic, superconducting assembly processes enabling scalable quantum hardware packaging.

Responsibilities
  • Lead development of cryogenic‑compatible assembly processes for 2D, 2.5D, and 3D quantum packaging platforms.
  • Define assembly schemes for:
    Flip‑chip / micro‑bump / superconducting bump attach Die‑to‑wafer (D2W), wafer‑to‑wafer (W2W), and hybrid bonding.
  • Ensure processes are optimized for low‑loss, superconducting signal paths and mechanical integrity at cryogenic temperatures.
  • Own assembly integration flows from incoming wafer/die through package build.
  • Coordinate process interactions across:
    Bump/interconnect teams, TSV/interposer integration, Substrate/package assembly.
  • Define and maintain process flow specifications, traveler flows, and assembly integration schemes.
  • Enable prototype builds, ensuring smooth execution through internal and external assembly lines.
  • Drive assembly readiness for new technologies, including tooling, materials, and process modules.
  • Support hands‑on build/debug during early development phases.
  • Develop and implement strategies to improve assembly yield and throughput; reduce defects (alignment, voiding, delamination, interconnect failures).
  • Lead failure analysis and root‑cause investigations for assembly‑related issues.
  • Work with test and systems teams to ensure assembled hardware meets: cryogenic reliability across thermal cycles; electrical and RF/microwave integrity requirements.
  • Support hardware bring‑up, validation, and debug in cryogenic environments (e.g., dilution refrigerators).
  • Evaluate and select assembly materials and interfaces (e.g., indium, superconducting metals, underfills, substrates) for cryogenic operation.
  • Work with equipment teams to define requirements for high‑precision alignment/bonding tools and cryogenic‑compatible materials handling.
  • Develop deep understanding of tool capability vs. quantum packaging requirements.
  • Collaborate with quantum device/qubit teams, packaging & integration engineers, cryogenic system and hardware teams.
  • Interface with OSATs, assembly partners, and suppliers to co‑develop and scale assembly processes.
  • Drive development of next‑generation assembly architectures for scaling qubit systems: high‑density interconnect co‑packaging, interposer‑based and 3D stacked integration.
  • Contribute to APPC / Quantum packaging roadmap and capability build‑out.
  • Generate and maintain assembly process flows, specifications, and integration guidelines.
  • Provide clear technical updates, data analysis, and reports to stakeholders.
  • Support IP generation, publications, and conference contributions.
  • Perform all activities in a safe and responsible manner and support environmental, health, safety & security requirements and programs.
  • Take part in hiring of other advanced packaging team members; mentor and guide new hires.
  • Other duties as assigned by manager.
Qualifications
  • Education – Master’s in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science or related field from an accredited degree program.
  • MS degree with at least 10 years of prior related work experience.
  • In‑depth knowledge of BEOL processes and integration, bump/wafer finish integration, wafer test/probe, OSAT collaboration, and package development & assembly.
  • Strong problem‑solving and technical troubleshooting skills including expertise in design of experiments.
  • Must have at least an overall 3.0 GPA and proven good academic standing.
  • Language Fluency – English (written & verbal).
  • Travel – up to 10%.
Preferred Qualifications
  • PhD education level preferred with at least 8 years of prior related work experience.
  • Demonstrated prior leadership experience in the workplace, school projects, competitions, etc.
  • Project management skills, ability to innovate and execute on solutions that matter;…
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