ASIC Design​/Verification Engineer

Position Overview:

We are looking for an experienced ASIC Design/Verification Engineer with extensive expertise in design verification. Proficiency in HDL (VHDL/Verilog) and HVL (System Verilog), along with experience in System Verilog Assertions (SVA) and UVM, is essential.

Key Responsibilities:

* Verify ASIC designs using VHDL/Verilog and System Verilog with coverage-driven methodologies.

* Implement System Verilog Assertions (SVA) and use UVM for thorough verification.

* Develop and monitor verification plans, refining strategies as necessary.

* Use scripting (Tcl, Python, Perl) to streamline verification workflows.

* Collaborate with design engineers to debug and ensure quality.

Required Qualifications:

* 9+ years of experience in ASIC verification.

* Expertise in HDL and HVL languages, System Verilog Assertions, and UVM.

* Knowledge of industry-standard interfaces.

Preferred

Skills:

* Proficiency in scripting languages.

* Strong communication skills for collaborative verification efforts.